TLC876C |
RFQ for TLC876C |
![]() |
| Technical/Catalog Information | TLC876CDBR |
| Vendor | Texas Instruments (VA) |
| Category | Integrated Circuits (ICs) |
| Number of Bits | 10 |
| Package / Case | 28-SSOP |
| Data Interface | Parallel |
| Packaging | Cut Tape (CT) |
| Sampling Rate (Per Second) | 20M |
| Operating Temperature | 0°C ~ 70°C |
| Voltage Supply Source | Analog and Digital |
| Number of Inputs and Type | 1 Single-Ended, Unipolar |
| Number of Converters | 9 |
| Power Dissipation (Max) | 150mW |
| Drawing Number | 296; 4040065; DB; 14, 16, 20, 24, 28, 30, 38 |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | TLC876CDBR TLC876CDBR 296 2940 1 ND 29629401ND 296-2940-1 |
| Product | Manufacturers | Pack | D/C |
| TLC876C | - | SOP28 | - |
The TLC876 is a CMOS, low-power, 10-bit, 20 MSPS analog-to-digital converter (ADC). The speed, resolution, and single-supply operation are suited for applications in video, multimedia, imaging, high-speed acquisition, and communications. The low-power and single-supply operation satisfy requirements for high-speed portable applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Force and sense connections to the reference inputs provide a more accurate internal reference voltage to the reference resistor string.
A standby mode of operation reduces the power to typically 15 mW. The digital I/O interfaces to either 5-V or 3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output data is straight binary coding.
A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the fifth stages operate on the four preceding samples.
Typical Application |
Features |
| Communications Multimedia Digital Video Systems High-Speed DSP Front-End ...TMS320C6x | 10-Bit Resolution 20 MSPS SamplingAnalog-to-Digital Converter (ADC)Power Dissipation . . . 107 mW Typ5-V Single Supply OperationDifferential Nonlinearity . . . ±0.5 LSB TypNo Missing CodesPower Down (Standby) ModeThree State OutputsDigital I/Os Compatible With 5-V or 3.3-VLogicAdjustable Reference InputSmall Outline Package (SOIC), Super SmallOutline Package (SSOP), or Thin SmallOutline Package (TSOP)Pin Compatible With the AnalogDevices AD876 |